Liquid crystal display device

ABSTRACT

In a liquid crystal display (LCD) device, two continuous frame image data to be displayed on a display unit are compared with each other by a comparator circuit, and horizontal and vertical synchronizing signals are regulated in accordance with a comparison result. That is, when the two frame image data coincide with each other, the horizontal and vertical synchronizing signals are not output to the display unit through the controller, in order to decrease the number of scannings of frames to be displayed. Also, when the LCD device has a backlight unit and two frame image data coincide with each other, the backlight unit is turned off.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a liquid crystal display devicecapable of reducing a consumption power.

[0002] As shown in FIG. 2, a liquid crystal display (LCD) controller 203is connected with an LCD unit 205, an image data memory 202, amicro-processing unit (MPU) 201 and a synchronizing signal generatorcircuit 204. Under commands of MPU 201, image data stored in the imagedata memory 202 is input to the LCD controller 203 and issignal-converted, so that the converted image data is displayed on theLCD unit 205.

[0003] In a conventional LCD controller, when the same (frame) imagedata is displayed on the LCD unit for a long time, (1) the display iscontinued, or (2) after an input interruption from a keyboard a mouse orthe like is monitored and a desired period of time elapses, driving of aliquid crystal is stopped after the displayed image data is restored inthe memory, or a backlight unit is turned off.

[0004] In the same frame image display for a long time, a method otherthan an image data restorage to the memory and a turning off of abacklight unit does not provide power saving of an LCD unit. Therefore,a frame image storage method for providing power saving without usingunnecessary memories is desired. Also, since a backlight unit is notalways included in all LCD devices, a method for providing power savingin a case wherein the same frame image is displayed for a long time,other than turning off of the backlight unit, is desired.

SUMMARY OF THE INVENTION

[0005] The object of the present invention is to solve the aboveproblem.

[0006] According to the present invention, a liquid crystal displaydevice of FIG. 1 includes, a micro-processing unit (MPU) 101 forcontrolling a whole peripheral circuit, an image data memory 102 capableof storing two frame image data, an image data arranging circuit 103 forarranging two frame image data, an image data comparator circuit 104capable of comparing two frame image data in bit units, a timer circuit106, a liquid crystal display (LCD) unit 110, an LCD controller 107 forcontrolling the LCD unit 110, a synchronizing signal generator circuit109 for generating synchronizing signals (vertical and horizontalsynchronizing signals), and a synchronizing signal regulating circuit108 for regulating vertical and horizontal synchronizing signals inaccordance with an output signal from the circuit 104. An output signalfrom the circuit 108 is input to the LCD controller 107, to controlsynchronizing signals to the LCD unit 110.

[0007] In the above structure, a peripheral circuit in an LCD devicerepresents a circuit having a function for driving a display portionconstructing the LCD unit. The display portion in the LCD device has astructure which pixels constructed by a liquid crystal arranged betweenat least one pair of electrodes are arranged at a matrix form. As astructure of the display portion, there is two types. One is a simplematrix type, and the other is an active matrix type.

[0008] Basically, an LCD unit includes analog buffers for driving eachliquid crystal pixel arranged at a matrix form, analog memories forstoring images to be displayed, and shift registers for generatingoperation timings of a matrix circuit in an X and Y directions. Also, aperipheral circuit in the LCD device includes an LCD controller forsupplying data and clocks for the shift registers of X and Y directionsto the LCD unit, a synchronizing signal generating circuit for supplyinghorizontal and vertical synchronizing signals and timing signals to theLCD controller, and an image data memory for storing images to bedisplayed.

[0009] The above structure can be used in a simple matrix type or anactive matrix type LCD device. A liquid crystal material to be used isnot limited to a specific material.

[0010] A memory element capable of storing two frame image data has afunction for storing two frame image data necessary to display twoframes. As the memory element, a video random access memory (VRAM) isused. The VRAM is of a dynamic random access memory (DRAM) and hasnormal parallel input and output ports, and further serial input andoutput ports.

[0011] Two frame image data stored in the image data memory 102 arecompared with each other in bit units by the image data comparatorcircuit 104, and then the circuit 104 outputs an output signalrepresenting a comparison result. In accordance with the output signal,the synchronizing signal regulator circuit 108 regulates horizontal andvertical synchronizing signals and supplies the regulated horizontal andvertical synchronizing signals to the LCD controller 107.

[0012] In a case wherein the same frame is displayed for a long time, ifthe number of scannings on a display portion (screen) of the LCD deviceis decreased, a consumption power can be reduced.

[0013] A time to decrease the number of scannings is set by the timercircuit 106, a time interval that characteristics of a liquid crystaldoes not deteriorate without applying an alternating voltage to a liquidcrystal in an LCD device, a refreshing time of a memory for storingimage data in a peripheral circuit of the LCD device, or a refreshingtime of an analog memory included in the LCD unit can be selected andset.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 shows a block diagram of a liquid crystal display (LCD)device according to an embodiment of the present invention;

[0015]FIG. 2 shows a block diagram of a convention LCD device;

[0016]FIG. 3 shows a block diagram of an LCD device according to anotherembodiment;

[0017]FIG. 4 shows a block diagram of an image data arranging circuit inthe LCD device of FIG. 3;

[0018]FIG. 5 shows a block diagram of an image data comparator circuitin the LCD device of FIG. 3; and

[0019]FIG. 6 shows a block diagram of an LCD device according to anotherembodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] [Embodiment 1]

[0021] In a peripheral circuit for a liquid crystal display (LCD) deviceas shown in FIG. 3, a video random access memory (VRAM) 301 is used asan image data memory element, an image data arranging circuit isconstructed by a first in first out (FIFO) circuit 302, an image datacomparator circuit is constructed by a comparator circuit 304, and asynchronizing signal regulator circuit is constructed by AND circuits305. Further, the LCD device includes an LCD controller 306, an LCD unit307 having a backlight unit 307 a, a timer 308 including a counter (notshown), and a synchronizing signal generator circuit 309.

[0022] An operation of the device of FIG. 3 is described below.

[0023] The LCD controller 306 performs image data read to the VRAM 301.Image data read out from the VRAM 301 is input to the FIFO circuit 302.

[0024]FIG. 4 shows a structure of the FIFO circuit 302. The FIFO circuit302 is constructed by an FIFO selector 401, FIFO0 402 and FIFO1 403, andflipflop (FF) circuits 404 and 405. The FIFO selector 401 switches tostore the first frame into the FIFO0 402 and store the second (next)frame into the FIFO1 403. When data is input to the FIFO1 403, the FIFO0402 and the FIFO1 403 are set to obtain an enable state with respect todata output. Data from the FIFO0 402 and the FIFO1 403 are synchronizedand output from the flipflop circuits 404 and 405 in accordance with astandard clock.

[0025] Output data signal from the FIFO circuit 302 is input to thecomparator circuit 304 as shown in FIG. 5. The comparator circuit 304includes two comparators 501 a and 501 b, two AND (gate) circuits 502 aand 502 b, two flipflop (FF) circuits 503 a and 503 b, and delaycircuits 504 a and 504 b for delaying a comparator circuit output. Eachtwo circuits are used to regulate horizontal and vertical synchronizingsignals. The delay circuit 504 a and 504 b are used to output signals insynchronous with a standard clock, to prevent an element delay or thelike in a case wherein a comparison result of two frame images is outputaccurately.

[0026] Image data signals in bit units with respect to two frame imagesare compared with each other by the comparators 501 a and 501 b. The ANDcircuits 502 a and 502 b output a low level (L) signal when the twoimage data signals coincide with each other, and output a high level (H)signal when the two image data signals are different from each other.The two output signals are synchronized with a standard clock by theflipflop circuits 503 a and 503 b and are output through the delaycircuits 504 a and 504 b. Therefore, in the comparator circuit 304, twoframe images are compared with each other and a level representingwhether or not the two frame images coincide with each other can bedetermined.

[0027] Output signals from the comparator circuit 304 are input to asynchronizing signal regulator circuit 305 constructed by the ANDcircuits. As shown in FIG. 3, in the AND circuits 305, an AND logicoperation is performed between the output signals from the circuit 304and the horizontal and vertical synchronizing signals from thesynchronizing signal generator circuit 309.

[0028] As described above, when two image data signals coincide witheach other, a low level (L) signal is output from the comparator circuit304. Therefore, when an AND logic operation is performed in the ANDcircuits 305, the horizontal and vertical synchronizing signals are notoutput from the AND circuits 305 to the LCD controller 306. Onlyvertical synchronizing signal may be not output.

[0029] On the other hand, when the two image data signals are differentfrom each other, a high level (H) signal is output from the comparatorcircuit 304. Therefore, when an AND logic operation is performed in theAND circuits 305, the horizontal and vertical synchronizing signals areoutput from the AND circuits 305 to the LCD controller 306.

[0030] In either of the above states, the horizontal and verticalsynchronizing signals are input to the LCD unit 307 through the LCDcontroller 306.

[0031] When two image data coincide with each other, the timer 308starts count and horizontal and vertical synchronizing signals aremaintained at the same state until a count value of the timer 308reaches a set value. The timer 308 is connected with the comparatorcircuit 304 through an interruption signal line 320. When the countvalue of the timer 308 reaches the set value, an interruption signaloutput from the timer 308 changes an output signal level of thecomparator circuit 304 into a high level (H).

[0032] Also, when two image data coincide with each other, since thetimer 308 is connected with the LCD unit 307 through a backlight unitswitch line 321, the timer 308 outputs a signal (having a level forturning off a backlight unit 307 a) to the backlight unit switch line321 after a count value of the timer 308 reaches an initial set value,so that the backlight unit 307 a of the LCD unit 307 can be turned off.When the timer 308 is reset, the level of the signal on the backlightunit switch line 321 is held to a level for turning on the backlightunit 307 a.

[0033] By the above operations, when the same frame images arecontinuous, turning on and off of the backlight unit 307 a can becontrolled.

[0034] [Embodiment 2]

[0035] In FIG. 6, VRAMs 602 and 603 are arranged as an image data memoryelement, and the first frame image and the second (next) frame image arestored in the VRAMs 602 and 603, respectively, by a VRAM input selector601 for selecting the VRAM 602 and 603. Since the VRAMs 602 and 603 areused in an LCD device of FIG. 6, the image data arranging circuit ofFIG. 1 is not necessary. The image data comparator circuit isconstructed by a comparator circuit 606, and the synchronizing signalregulator circuit is constructed by AND (gate) circuits 607. Further,the LCD device includes a VRAM output selector 604, an LCD controller608, an LCD unit 609 having a backlight unit 609 a, a timer circuit 610and a synchronizing signal generator circuit 611.

[0036] An operation of the LCD device of FIG. 6 is described.

[0037] Continuous image data are input to the VRAM input selector 601from a MPU bus connected with a MPU (not shown). An even frame image isstored in the VRAM 602, and an odd frame image is stored in the VRAM603.

[0038] The image data stored in the VRAMs 602 and 603 are input to thecomparator circuit 606 and the VRAM output selector 604. The VRAM outputselector 604 is a circuit for alternately reading out the image datafrom VRAMs 602 and 603 in response to a data readout signal from the LCDcontroller 608.

[0039] The comparator circuit 606 is the same structure as thecomparator circuit 304 and is shown in FIG. 5. Two frame image data (inbit units) read out from the VRAMs 602 and 603 are compared with eachother by the comparators 501 a and 502 b. In the comparators 501 a and501 b, when two image data signals coincide with each other, a low level(L) signal is output, and when the two image data signals are differentfrom each other, a high level (H) signal is output. Two output signalsare synchronized with a standard clock by the flipflop circuits 503 aand 503 b and output through the delay circuits 504 a and 504 b forcomparator circuit delay.

[0040] By the above operation, a level whether or not two frame imagescoincide with each other can be determined.

[0041] Output signals from the comparator circuit 606 are input to thesynchronizing signal regulator circuit 607. As shown in FIG. 6, an ANDlogic operation between the output signal from the circuit 606 andhorizontal and vertical synchronizing signals from the synchronizingsignal generator circuit 611 is performed in the AND circuits 607.

[0042] As described above, when two image data signals coincide witheach other, a low level (L) signal is output from the comparator circuit606. Therefore, when an AND logic operation is performed in the ANDcircuits 607, the horizontal and vertical synchronizing signals are notoutput from the AND circuits 607 to the LCD controller 608. Onlyvertical synchronizing signal may be not output.

[0043] On the other hand, when the two image data signals are differentfrom each other, a high level (H) signal is output from the comparatorcircuit 606. Therefore, when an AND logic operation is performed in theAND circuits 607, the horizontal and vertical synchronizing signals areoutput from the AND circuits 607 to the LCD controller 608.

[0044] In either of the above states, the horizontal and verticalsynchronizing signals are input to the LCD unit 609 through the LCDcontroller 608.

[0045] When two image data coincide with each other, the timer circuit610 starts count and horizontal and vertical synchronizing signals aremaintained at the same state until a count value of the timer circuit610 reaches a set value. The timer circuit 610 is connected with thecomparator circuit 606 through an interruption signal line 620. When thecount value of the timer circuit 610 reaches the set value, aninterruption signal output from the timer circuit 610 changes an outputsignal level of the comparator circuit 606 into a high level (H).

[0046] Also, when the two image data coincide with each other, since thetimer circuit 610 is connected with the LCD unit 609 through a backlightunit switch line 621, the timer circuit 610 outputs a signal (having alevel for turning off the backlight unit 609 a) to the backlight unitswitch line 621 after a count value of the timer circuit 610 reaches aninitial set value, so that the backlight unit 609 a of the LCD unit 609can be turned off. When the timer circuit 610 is reset, the level of thesignal on the backlight unit switch line 621 is held to a level forturning on the backlight unit 609 a.

[0047] By the above operations, when the same frame images arecontinuous, turning on and off of the backlight unit 609 a can becontrolled.

[0048] According to the present invention, when the same frame imagesare continuous, synchronizing signals (or only vertical synchronizingsignal) are not output to a liquid crystal display device. As a result,the number of scannings of frames to be displayed on the liquid crystaldisplay device is decreased and the backlight unit is turned off, sothat consumption power of the liquid crystal display device can bereduced.

What is claimed is:
 1. A method of driving a display device comprising:storing a first image data; storing a second image data; comparing thefirst image data and the second image data; supplying horizontal andvertical synchronizing signals to a controller from a synchronizingsignal generator circuit if the first image data and the second imagedata are different from each other; and halting an output of thevertical synchronizing signals from the synchronizing signal generatorcircuit if the first image data and the second image data coincide witheach other.
 2. The method according to claim 1 wherein said displaydevice is a liquid crystal device.
 3. A method of driving a displaydevice comprising: storing a first image data; storing a second imagedata; comparing the first image data and the second image data;supplying horizontal and vertical synchronizing signals to a controllerfrom a synchronizing signal generator circuit if the first image dataand the second image data are different from each other; and halting anoutput of the horizontal and vertical synchronizing signals from thesynchronizing signal generator circuit if the first image data and thesecond image data coincide with each other.
 4. The method according toclaim 3 wherein said display device is a liquid crystal device.
 5. Amethod of driving a display device comprising: storing a first imagedata; storing a second image data; comparing the first image data andthe second image data; supplying horizontal and vertical synchronizingsignals to a peripheral circuit from a synchronizing signal generatorcircuit if the first image data and the second image data are differentfrom each other; and halting an output of the vertical synchronizingsignals from the synchronizing signal generator circuit if the firstimage data and the second image data coincide with each other.
 6. Themethod according to claim 4 wherein said display device is a liquidcrystal device.
 7. A method of driving a display device comprising:storing a first image data; storing a second image data; comparing thefirst image data and the second image data; supplying horizontal andvertical synchronizing signals to a peripheral circuit from asynchronizing signal generator circuit if the first image data and thesecond image data are different from each other; and halting an outputof the horizontal and vertical synchronizing signals from thesynchronizing signal generator circuit if the first image data and thesecond image data coincide with each other.
 8. The method according toclaim 7 wherein said display device is a liquid crystal device.
 9. Amethod of driving a display device comprising: storing a first imagedata; storing a second image data; comparing the first image data andthe second image data; supplying horizontal and vertical synchronizingsignals to a display portion if the first image data and the secondimage data are different from each other; and halting the supplying ofthe vertical synchronizing signals to the display portion if the firstimage data and the second image data coincide with each other.
 10. Themethod according to claim 6 wherein said display device is a liquidcrystal device.
 11. The method according to claim 8 wherein said displayportion is a simple matrix type.
 12. The method according to claim 8wherein said display portion is an active matrix type.
 13. A method ofdriving a display device comprising: storing a first image data; storinga second image data; comparing the first image data and the second imagedata; supplying horizontal and vertical synchronizing signals to adisplay portion if the first and second image data are different fromeach other; and halting the supplying of the horizontal and verticalsynchronizing signals to the display portion if the first image data andthe second image data coincide with each other.
 14. The method accordingto claim 13 wherein said display device is a liquid crystal device. 15.The method according to claim 13 wherein said display portion is asimple matrix type.
 16. The method according to claim 13 wherein saiddisplay portion is an active matrix type.
 17. A display devicecomprising: a display portion; a first VRAM for storing a first imagedata; a second VRAM for storing a second image data; a comparatorcircuit for comparing the first and second image data; a synchronizingsignal regulator circuit for selectively outputting horizontal andvertical synchronizing signals depending upon an output from thecomparator.
 18. The display device according to claim 17 wherein saiddisplay device is a liquid crystal device.
 19. The display deviceaccording to claim 17 wherein said synchronizing signal regulatorcircuit comprises AND circuits.
 20. A display device comprising: adisplay portion; a first VRAM for storing a first image data; a secondVRAM for storing a second image data; a comparator circuit for comparingthe first and second image data; a synchronizing signal regulatorcircuit for selectively outputting vertical synchronizing signalsdepending upon an output from the comparator.
 21. The display deviceaccording to claim 20 wherein said display device is a liquid crystaldevice.
 22. The display device according to claim 20 wherein saidsynchronizing signal regulator circuit comprises AND circuits.
 23. Adisplay device comprising: a display portion; at least one vide randomaccess memory for storing at least first and second image data; acomparator circuit for comparing the first and second image data; asynchronizing signal generator circuit for outputting horizontalsynchronizing signals and vertical synchronizing signals; asynchronizing signal regulator circuit for receiving an output signalfrom the comparator circuit and the horizontal and verticalsynchronizing signals; and a controller operationally connected to thesynchronizing signal regulator circuit.